[[["容易理解","easyToUnderstand","thumb-up"],["確實解決了我的問題","solvedMyProblem","thumb-up"],["其他","otherUp","thumb-up"]],[["難以理解","hardToUnderstand","thumb-down"],["資訊或程式碼範例有誤","incorrectInformationOrSampleCode","thumb-down"],["缺少我需要的資訊/範例","missingTheInformationSamplesINeed","thumb-down"],["翻譯問題","translationIssue","thumb-down"],["其他","otherDown","thumb-down"]],["上次更新時間：2025-08-19 (世界標準時間)。"],[[["\u003cp\u003eThe Performance Monitoring Unit (PMU) is a hardware component in the CPU core that monitors processor code execution and can be enabled in C4A or C4 virtual machines (VMs) to access performance counters.\u003c/p\u003e\n"],["\u003cp\u003eEnabling the PMU allows users to measure low-level processor events, such as branch mispredictions and cache misses, using performance-monitoring software to help optimize workloads like HPC and ML.\u003c/p\u003e\n"],["\u003cp\u003eThe PMU supports three types of performance monitoring events: Architectural, which measures general events like branch instructions and core cycles; Standard, which also measures local events within the CPU core; and Enhanced, which additionally includes local events outside the CPU core.\u003c/p\u003e\n"],["\u003cp\u003eThe PMU can only be enabled on Google Axion C4A VMs or Intel Xeon Scalable Processor (Emerald Rapids) 5th generation C4 VMs, with the Enhanced PMU type limited to C4 machines with 96 or 192 vCPUs.\u003c/p\u003e\n"],["\u003cp\u003eThere are no additional costs associated with enabling or disabling the PMU in a VM.\u003c/p\u003e\n"]]],[],null,["*** ** * ** ***\n\nThis document explains the behavior, billing, and limitations of the performance\nmonitoring unit (PMU) in Compute Engine. To learn how to enable the PMU in a\nC4A or C4 virtual machine (VM) instance, see\n[Enable the PMU in VMs](/compute/docs/enable-pmu-in-vms).\n\nThe PMU is a hardware component within the CPU core that monitors how the\nprocessor runs code. By enabling the PMU in a C4A or C4 VM, you can access the\nperformance counters in the PMU using performance-monitoring software. This\napproach lets you optimize performance-sensitive workloads, such as high\nperformance computing (HPC) or machine learning (ML) workloads, by helping you\nidentify and address performance bottlenecks in your applications.\n\nHow the PMU works\n\nThe PMU is composed of a set of hardware counters called performance monitoring\ncounters (PMCs). These counters are\n[model-specific registers](https://en.wikipedia.org/wiki/Model-specific_register)\nthat count each time a low-level processor event, such as a branch misprediction\nor cache miss, occurs within the CPU. You can read and configure PMCs in the PMU\nby using performance-monitoring software such as\n[Intel VTune Profiler](https://www.intel.com/content/www/us/en/developer/tools/oneapi/vtune-profiler.html).\n\nBy default, the PMU is disabled within VMs. To enable it, specify the types of\nlow-level CPU events to track by enabling one of the following PMU types:\n\n- **Architectural (`ARCHITECTURAL`)**: You can measure the following\n architectural performance events:\n\n - **Branch instructions retired**: The number of branch instructions\n retired. Use this event to measure your code's execution and identify\n potential performance bottlenecks.\n\n - **Branch misses retired**: The number of branch instructions that were\n mispredicted, causing the processor to stall and discard fetched\n instructions. If you see a high number for this event, then you can\n likely optimize the CPU performance.\n\n - **Instructions retired**: The number of instructions the CPU\n successfully processes. Use this event to measure the CPU's instruction\n throughput.\n\n - **Top down slots**: The number of available slots within a processor's\n pipeline that are used to simultaneously execute instructions. Use this\n event to understand how efficiently your code is using the processor's\n resources.\n\n - **Unhalted core cycles**: The number of core cycles when the thread is\n not halted---for example, due to power management or interrupts. Use\n this event to evaluate the overall usage of the processor.\n\n - **Unhalted reference cycles** : The number of reference cycles when the\n core is not halted---for example, when fetching data or\n instructions. The core is halted when it runs the\n [`HLT` or `MWAIT` instructions](https://en.wikipedia.org/wiki/HLT_(x86_instruction)).\n Reference cycles operate at a fixed frequency, providing a stable time\n reference even when the speed of the processor changes to preserve\n energy. Use this event to measure the time spent on a task and identify\n performance bottlenecks in your code.\n\n- **Standard (`STANDARD`)**: You can measure all events from the Architectural\n PMU type and any local events inside the CPU core, including level 2 (L2)\n cache events.\n\n- **Enhanced (`ENHANCED`)**: You can measure all events from the Standard PMU\n type, any local events outside the CPU core, including level 3 (L3) cache\n events.\n\nAfter you enable the PMU in a VM, the PMU runs in the background, continuously\nmonitoring performance events using PMCs. You can optionally configure\nthresholds for specific PMCs using your preferred performance-monitoring\nsoftware. If a PMC exceeds its designated threshold, then the PMU notifies the\nsoftware.\n\nLimitations\n\nThe PMU has the following limitations:\n\n- You can only enable the PMU in the following CPU platforms:\n\n | | **CPU platform** | **Supported machine series** | **Supported performance events** |\n |---|---------------------------------------------------------------|----------------------------------------------------------|----------------------------------------------------------------------------------------------------------|\n | | Google Axion™ Processor | [C4A](/compute/docs/general-purpose-machines#c4a_series) | [Arm Neoverse V2 PMU Guide](https://developer.arm.com/documentation/109709/latest/) |\n | | Intel Xeon Scalable Processor (Emerald Rapids) 5th generation | [C4](/compute/docs/general-purpose-machines#c4_series) | [emeraldrapids_core.json](https://github.com/intel/perfmon/blob/main/EMR/events/emeraldrapids_core.json) |\n\n- You can enable the Enhanced PMU type only in VMs that use a C4 machine type\n with 96 or 192 vCPUs.\n\nPricing\n\nThere are no costs associated with enabling or disabling the PMU in a VM.\n\nWhat's next\n\n- [Enable the PMU in VMs](/compute/docs/enable-pmu-in-vms)\n\n- [Enable the PMU in Google Kubernetes Engine clusters](/kubernetes-engine/docs/how-to/analyzing-cpu-performance-using-pmu)"]]
